TSMC recently announced at a North American technology seminar the defect density (D0) of its N2 (2nm) process technology compared to its predecessor processes at the same stage. According to the company, the defect density of N2 process is lower than that of N3 (3nm), N5 (5nm), and N7 (7nm) manufacturing nodes. In addition, the slide shows that TSMC's N2 process is still two quarters away from mass production, which means TSMC is expected to start producing 2nm chips by the end of the fourth quarter of 2025 as expected.
Although TSMC's N2 process is the company's first process technology to adopt full gate ring (GAA) nanosheet transistors, the defect density of this node is lower than the previous generation process at the same stage, two quarters ahead of mass production (MP). The previous generation processes - N3/N3P, N5/N4, and N7/N6- all used mature fin field-effect transistors (FinFETs). Therefore, although N2 is TSMC's first node to adopt GAA nanosheet transistors, its defect density reduction is greater than the previous generation process before entering the mass production (HVM) milestone.
This chart depicts the variation of defect density over time, spanning from three quarters before mass production to six quarters after mass production. Among all displayed nodes - N7/N6 (green), N5/N4 (purple), N3/N3P (red), and N2 (blue) - defect density significantly decreases with increasing yield, but the rate of decrease varies depending on the complexity of the nodes. It is worth noting that N5/N4 is the most active in reducing early defects, while the yield improvement of N7/N6 is relatively gentle. The initial defect level of the N2 curve is higher than that of N5/N4, but then sharply decreases, which is very close to the defect reduction trajectory of N3/N3P.
The slide emphasizes that yield and product diversity remain key driving factors for accelerating defect density improvement. Greater production and diversified products using the same process can identify and correct defect density and yield issues faster, enabling TSMC to optimize defect learning cycles. TSMC stated that its N2 manufacturing technology has obtained more new chips than its predecessor technology (as TSMC now produces N2 chips for smartphone and high-performance computing (HPC) customers at risk), and the defect density decline curve basically confirms this.
Considering the risk factors brought about by the introduction of a new transistor architecture, it is particularly important for the defect reduction rate of N2 to remain consistent with previous FinFET based nodes. This indicates that TSMC has successfully transferred its process learning and defect management expertise to the new GAAFET era without encountering significant setbacks.
