An Intel director believes that future transistor designs may reduce the demand for advanced lithography equipment in manufacturing high-end semiconductors.
ASML's extreme ultraviolet (EUV) lithography machines are the backbone of modern advanced chip manufacturing, as they enable companies such as TSMC to print extremely small circuits on silicon wafers. It is understood that EUV technology is extremely complex, and an EUV lithography equipment requires the collaborative support of multiple interdisciplinary technologies to achieve cost-effective mass production capabilities. ASML had researched other technological paths many years ago, but ultimately abandoned them. There is currently no reliable data indicating that mature EUV systems are under development.
However, the Intel director believes that future transistor designs, including surround gate field-effect transistors (GAAFETs) and complementary field-effect transistors (CFETs), will rely more on post photolithography manufacturing steps and reduce the overall importance of photolithography technology in manufacturing high-end chips.
An Intel director who declined to be named stated that future transmission designs will reduce reliance on advanced lithography equipment and rely more on etching technology. Although lithography machines are the most popular chip manufacturing equipment, manufacturing chips also involves other steps.
Photolithography is the first step of the process, which transfers the design onto the wafer. Then, these designs are fixed through processes such as deposition and etching. During the deposition process, chip manufacturers deposit materials onto wafers, while etching selectively removes these materials to form patterns of chip transistors and circuits.
Intel directors stated that new transistor designs such as GAAFET and CFET can reduce the importance of lithography machines in the chip manufacturing process. These machines, especially EUV lithography machines, play a crucial role in manufacturing 7nm and advanced technology chips due to their ability to transfer or print small circuit designs on wafers.
After the design transfer, etching will remove excess material from the wafer and ultimately complete the design. Currently, most transistor designs follow the FinFET model, where the transistor is connected to the bottom insulation material and controlled by a gate that controls its internal current. Newer designs, such as GAAFET, wrap the gate around the transistor and place the transistor groups in parallel. Ultra high end transistor design, such as CFET, stacks transistor groups together to save space on the wafer.
Intel directors stated that removing excess material from the wafer is crucial as GaaFET and CFET designs "wrap" the gate from all directions. This "wrapping" requires chip manufacturers to horizontally remove excess material, so instead of increasing the time the wafer spends on the lithography machine to reduce feature size, it is better to focus more on removing material through etching.
